A dynamic random access memory (DRAM) device is commonly used in electronic systems to store data. A typical DRAM device will have one region corresponding to a memory array and another region peripheral to the memory array in which logic or other circuitry is to be formed. Each memory cell generally consisting of a capacitor coupled through a transistor gate electrode or wordline stack to a bit or digit line.
Continuing advances in miniaturization and densification of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. With shrinkage of the cell size, maintaining a sufficient amount of cell charge storage capacitance is a challenge in a DRAM construction.
Several techniques have been developed to increase the storage capacity of a capacitor in a limited space. One such technique is to fabricate a double-sided container capacitor, which involves forming a cup-shaped bottom electrode in an opening formed in a sacrificial insulative layer, which is typically a doped oxide layer such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or borosilicate glass (BSG), for example. The doped oxide layer is etched back to expose the exterior surface of the bottom electrode, and a dielectric material and then a top electrode layer are deposited to form the container capacitor structure. Using a double-sided bottom electrode provides a higher surface area for increased capacitance.
A draw-back of the foregoing process is that exposure of both the interior and exterior surfaces of a “ee-standing” container, particular a container having a high aspect ratio, can render the container structurally weak and subject to collapse during exposure to a wet-etch process to remove the doped oxide material from adjacent the bottom electrode. To overcome that problem, a silicon nitride (SiN) lattice is formed over the structure to support and hold adjacent capacitor containers together.
Steps in a prior art method of forming a double-sided container capacitor utilizing a SiN lattice are illustrated with reference to FIGS. 1-6.
FIG. 1, which depicts a wafer fragment 10 at a preliminary processing step, includes a substrate 12 with active areas 14. A relatively thick layer of a doped oxide insulative layer 16 (e.g., PSG) has been formed over the substrate 12, having an exemplary thickness of about 14,000-18,000 Å. The substrate 12 is divided into three defined regions (indicated by dashed lines), including a memory cell array region 18, a peripheral logic circuitry (peripheral) area 20 where control circuitry (i.e., logic circuitry, etc.) associated with the control of data flow to and from memory devices associated with the memory cell array is formed, and intermediate region 22 corresponding to an area between the memory cell array region 18 and the peripheral area 20.
In a first step depicted in FIGS. 1 and 1A, a blanket layer of silicon nitride (SiN) 24, which is typically about 1,200-1,400 Å thick, is deposited over the doped oxide insulative layer 16, and the SiN layer 24 and doped oxide layer 16 over the memory array region 18 are etched to form openings (capacitor containers) 26, for example, by successive standard dry etch processes, through openings in patterned photoresist masks. A trench 28, which can be etched simultaneously with the capacitor containers 26, is also formed within the intermediate region 22 between the memory cell array region 18 and the peripheral area 20. The resulting structure, depicted in FIGS. 2 and 2A, provides a SiN lattice portion 30, which functions as a retaining structure to support adjacent capacitor containers 26.
Conventionally, the SiN layer 24 is formed using a high temperature deposition process at about 700° C. to 780° C. However, high process temperatures can be detrimental, and the trend for future generation devices is the use of low temperature depositions of about 600° C. or less due to thermal budget limitations and to avoid damaging existing features. One such process is an LPCVD process using hexachlorodisilane (HCD, (Si2Cl6) at a low temperature (about 600° C. or less) to deposit HCD silicon nitride as the SiN layer 24.
An electrically conductive layer 32 is then formed within the container openings 26 and the trench 28, as shown in FIGS. 3 and 3A. Generally, the thickness of the conductive layer 32 is about 200-400 Å. The conductive layer 32 can comprise, for example, conductively doped silicon, metal, and metal-containing compounds, which in the present example, is titanium nitride (TiN). The TiN layer 32 within the container openings 26 ultimately forms the lower electrode of the container capacitor structure. The container constructions can be considered to comprise an inner surface 34 within the container openings 26 and an exterior or outer surface 36 laterally opposed to the inner surface 34.
Referring to FIGS. 4 and 4A, the TiN layer 32 is then removed from over the surface of the structure to expose the SiN layer 24 (including the SiN lattice portion 30) and to electrically isolate the TiN layer 32 within the container openings 26 from one another, for example, by chemical-mechanical polishing, thus forming the bottom electrodes of the container capacitor structures.
After removal of the TiN layer 32 from outside the openings 26, a photoresist mask layer 38 is blanket coated over the memory cell array region 18, peripheral region 20, and intermediate area 22 into the openings 26 and the trench 28. As illustrated in FIGS. 5 and 5A, the photoresist mask layer 38 is patterned over the memory cell area region 18 to expose bands of the SiN lattice portion 30 between adjacent pairs of container openings 26. Portions of the TiN layer 32 (bottom electrodes) in the openings 26 and trench 28 are shown in phantom to indicate that the masking layer covers such portions.
A pattern is transferred from the photoresist mask layer 38 to the SiN layer 24, and the photoresist mask layer 38 is removed. A conventional dry etch can then be performed to selectively remove unmasked portions of the SiN lattice portion 30 and expose the underlying doped oxide insulative layer 16 of between pairs of capacitor container rows, with the remaining portions of the SiN lattice portion 30 interconnecting and holding adjacent pairs of capacitor containers 26 together, resulting in the structure shown in FIGS. 6 and 6A.
Next, the doped oxide layer 16 in the memory cell array region 18 is isotropically wet etched selectively relative to the SiN lattice portion 30 and the TiN layer 32 within the openings 26 to expose all or part of the outer surfaces 36 of the TiN bottom electrode 32. Since it is not desirable to remove the doped oxide layer 16 within the peripheral area 20, the SiN layer 24 is maintained over that area. The TiN layer 32 within the trench 28 together with the SiN layer 24 over the peripheral area 20 function together as a barrier to prevent wet etch solutions from seeping into the doped oxide layer 16 within the peripheral area 20 during the etching of the doped oxide layer 16 within the memory cell array region 18, which could damage circuitry (not shown) associated with the peripheral area 20.
In etching the doped oxide layer 16, which is very thick compared to the thin SiN layer 24, the SiN layer (including the SiN lattice portion 30) will be etched by the time that the thickness of the doped oxide insulative layer 16 is removed if the selectivity of the etch solution for the doped oxide material is not extremely high. Current processes for selectively etching doped oxides (e.g., PSG) relative to silicon nitride utilize wet etchants.
One such etchant is a mixture of acetic acid (“ac”) and hydrofluoric acid (HF, 49% by wt.), typically in a 30:1 (v/v) ac:HF ratio, which provides a selective etch of PSG relative to silicon nitride of about 250:1-400:1. However, the etch rate is relatively slow at about 2,000 Å/minute, which impacts processing throughput.
Another conventional etchant for selectively etching a doped oxide is a 10:1 (v/v) ratio of water (deionized water, DI) and HF (49% by wt.). Although a 10:1 DI:HF etchant solution provides an etch rate of about 9,000 Å/minute, the selectivity for a doped oxide relative to silicon nitride is only about 200:1 for high temperature nitrides such as DCS (dichlorosilane) silicon nitride, and only about 50-55:1, at best for low temperature silicon nitrides such as HCD silicon nitride. Thus, current H2O:HF etch chemistries for high temperature silicon nitrides do not provide the selectivity of doped oxide relative to low temperature silicon nitrides that is needed in the fabrication of container constructions.
Consequently, etching away a relatively thick, doped oxide layer (e.g., PSG) to expose the bottom electrode wall requires an etchant with a high selectivity to relative to silicon nitride and other materials such as the bottom electrode material (e.g., TiN) and polysilicon, which form portions of the capacitor structure.